Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell (e.g., floating gate) that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage nodes (e.g., floating gates or trapping layers) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR Flash and NAND Flash. The designation is derived from the logic used to read the devices. FIG. 1 illustrates a NAND type flash memory array architecture 100 wherein the floating gate memory cells 102 of the memory array are arranged in a logical matrix of rows and columns. The memory cells 102 of the array are also arranged together in strings (e.g., NAND strings), typically of 8, 16, 32, or more each, where the memory cells in a string are connected together in series, source to drain, between a source line 128 and a data line 130, often referred to as a bit line. The array is then accessed by a row decoder activating a logical row of floating gate memory cells by selecting a particular access line, often referred to as a word line WL7-WL0 1128-1121, connected to their control gates. As is known to those skilled in the art, the number of word lines and bit lines might be much greater than those shown in FIG. 1.
In addition, bit lines BL0-BL3 1301-1304 can also be driven high or low depending on the operation being performed. For example, during a typical read operation, even numbered bit lines BL0 1301 and BL2 1303, are pre-charged by sense devices 1381 and 1383, respectively, to a particular bias level. Odd numbered bit lines BL1 1302 and BL3 1304 are driven low to a common ground connection GND 146, such as through gates 1561 and 1562. In a subsequent read operation, even numbered bit lines may be driven to GND 146 while odd numbered bit lines are read. The bit line select gates 1561-1562, 1601-1602 thereby allow for either the even or odd bit lines to be coupled to a common ground potential node, GND 146. Select gates 156/160, are typically large, high voltage devices which are located outside of the array. By coupling every other bit line (e.g., alternate bit lines) to GND 146 during a read operation, the grounded bit lines serve as a shield (e.g., through capacitive coupling) between to the two adjacent strings (e.g., precharged bit lines) of memory cells being read, such as 1641 and 1643, for example.
Bit lines BL0-BL3 1301-1304 are coupled to sensing devices (e.g., sense amplifiers) 1381-1384 that detect the state of each cell by sensing voltage on a particular bit line 1301-1304. Word lines WL7-WL0 1128-1121 select the individual memory cells (e.g., 1641-1644) in the series strings to be written to, verified or read from and operate the remaining memory cells in each series string in a pass through mode. Each series string of memory cells is coupled to a source line 128 by a source select gate 106 and to an individual bit line BL0 1301 by a drain select gate 104, for example. The source select gates, such as 106, are controlled by a source select gate control line SG(S) 110 coupled to their control gates. The drain select gates, such as 104, are controlled by a drain select gate control line SG(D) 108.
Memory cells 102 can be what are known in the art as Single Level Memory Cells (SLC) or Multilevel Memory Cells (MLC). SLC and MLC memory cells are assigned a data state (e.g., as represented by one or more bits) to a specific range of threshold voltages (Vt) stored on the memory cell. Single level memory cells (SLC) permit the storage of a single binary digit (e.g., bit) of data on each memory cell. Meanwhile, MLC technology permits the storage of two or more binary digits per cell (e.g., 2, 4, 8, 16 bits), depending on the quantity of Vt ranges assigned to the cell and the stability of the assigned Vt ranges during the lifetime operation of the memory cell. The number of Vt ranges (e.g., levels), used to represent a bit pattern comprised of N-bits is 2N, where N is an integer. For example, one bit may be represented by two levels, two bits by four levels, three bits by eight levels, etc. Some memory cells can store fractional numbers of bits, such as 1.5 bits per cell (e.g., MLC (three level)). A common naming convention is to refer to SLC memory as MLC(two level) memory as SLC memory utilizes two Vt ranges in order to store one bit of data as represented by a 0 or a 1, for example. MLC memory configured to store two bits of data can be represented by MLC(four level), three bits of data by MLC(eight level), etc.
FIG. 2 illustrates an example of Vt ranges 200 for a MLC(four-level) (e.g., 2-bit) memory cell. For example, a cell may be assigned a Vt that falls within one of four different Vt ranges 202-208 of 200 mV, each being used to represent a data state corresponding to a bit pattern comprised of two bits. As one example, if the voltage stored on the cell is within the first of the four Vt ranges 202, the cell in this case is storing a logical ‘11’ state and is typically considered the erased state of the cell. If the voltage is within the second of the four Vt ranges 204, the cell in this case is storing a logical ‘10’ state. A voltage in the third Vt range 206 of the four Vt ranges would indicate that the cell in this case is storing a logical ‘00’ state. Finally, a Vt residing in the fourth Vt range 208 indicates that a logical ‘01’ state is stored in the cell.
Referring again to FIG. 1, during a typical read operation of the memory array 100, NAND strings of memory cells coupled to even numbered bit lines (e.g., 1301, 1303) are read, followed by a read operation of the NAND strings coupled to odd numbered bit lines (e.g., 1302, 1304.) During a read operation, bit lines to be read (e.g., not grounded to GND 146) are precharged to a particular bias level, such as 0.5V, for example. A read operation may be performed of memory cells 1641-1644 of the row (e.g., word line) WL4 1125, for example. As the read operation is performed, the bit line being read can be discharged into the SRC line 128. As a result, the SRC line 128 may experience what is referred to as source line bounce wherein the bias level of the source line rises in response to the bit lines being discharged into the SRC line 128. This source line bounce can thereby introduce errors during a read operation of the memory.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to reduce the effects of source line bounce while sensing memory cells in a memory device.